The CICA Windows Explosion!

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****************************************************************** DESIGN CENTER - 5.4 RELEASE MICROSOFT WINDOWS EVALUATION VERSION ****************************************************************** This file describes enhancements and modifications made to the 5.4 release of the Design Center. Also included in this file is information which was not included in the documentation set provided with the software. ****************************************************************** CONTENTS ****************************************************************** Part 1. New Features 2 Part 2. Evaluation Versions 3 Part 3. General 4 3.1. Version Interchangeability-Stand Alone Schematics 4 3.2. New Command Line Option: -i 4 Part 4. PSpice 4 4.1. PSpice Command Line Options 4 4.2. PWL Form for I and V Devices 5 4.3. PWL Syntax 5 4.4. PWL Usage Limitations 5 4.5. New Digital Simulator Operation 6 4.6. New "O" Device Parameter and Operation 6 4.7. Digital Worst-Case Timing Analysis Enhancement 7 4.8. New Example Circuit 7 Part 5. Probe 8 5.1. Probe Command Line Options 8 5.2. Marching Waveforms 8 5.2.1. Marching Waveforms During Multiple-Run Analyses 8 5.2.2. Known Problems 9 5.3. Cut, Copy, and Paste Commands 9 5.3.1. Using the Clipboard Data 9 5.3.2. Pasting Objects from the Tools/Label Menu 9 5.4. Goal Function File 9 Part 6. Schematics 10 6.1. Using Schematics Created with Version 5.3 and Earlier 10 6.2. Schematics Netlister 10 6.3. New Symbols 10 6.3.1. STIM Symbols - "source.slb" 10 6.3.2. PRINT AND PLOT Symbols - "special.slb" 11 6.3.3. Analog Devices with Visible Pin Numbers - "analog_p.slb" 11 6.3.4. Time-Dependent Switches 12 6.4. Autosave 12 6.5. Marker Support 12 6.5.1. Implementation 13 6.6. Probe Setup Options in Schematics 13 6.6.1. Restore Last Probe Session 13 6.6.2. Show All Markers 13 6.6.3. Show Selected Markers 13 6.6.4. None 13 6.7. Changes to the "msim.ini" File 13 6.8. Accelerator Key Changes 14 6.9. Font-Related Issues 14 6.9.1. Using the RASTERFONT=ON/OFF Switch 14 6.9.2. Using Adobe Type Manager with Schematics 14 Part 7. Device Equations Option 14 Part 8. Polaris Signal Integrity 15 Part 9. Intel IBIS Model Support 16 Part 10. New Libraries and Devices 20 10.1. New Library - "AMP.LIB" 20 10.2. New Devices - "LIN_TECH.LIB" Library 21 10.3. New Devices in Other Libraries 22 Part 11. MODTOMDT Utility 22 ****************************************************************** Part 1. New Features ****************************************************************** The following list of new features is applicable to the production version of the Design Center for Windows. Some features are not available for the evaluation version. DESIGN CENTER * Solaris support. * Mentor integration. * Expanded libraries now with over 5,300 analog and 1,700 digital devices. * PC Network license configuration. * New evaluation version of the Design Center with digital emphasis including an increase on limits. SCHEMATICS * Extended support for external board layout packages: CADStar, P- CAD, and Tango. * Stand-alone Schematics package. * The capability to print a selected area. * An autosave feature that performs an automatic save of the schematic file every 10 minutes (by default), if there are any modifications. The default time interval can be overwritten by the user. * Netlist creation for the entire design from any level of hierarchy. * Improved attribute handling features in the Attributes dialog, such as the ability to exclude non-changeable attributes and system attributes. * Marker support of PSpice and Probe output variables for AC analysis specific elements, such as magnitude, DB (magnitude in decibels), P (phase), and G (group delay). * The assignment and re-assignment of user-defined attribute text layers, which allows the user to group attributes and perform actions (such as Set Display Level) on the selected group. * Vertical and horizontal alignment of selected items. All selected items can be moved so that their origins, leftmost endpoints, or centers are vertically or horizontally aligned. PSPICE * Improved speed with a 32-bit compiler implementation. * Lossy transmission line enhancements; the K device has been extended to allow systems of coupled transmission lines to be simulated. * Repetitions in PWL waveform specifications. * Improved flip-flops/constraint consistency. PROBE * Speed improvements. * Marching Waveforms. * Scroll bars in Probe for enhancement of viewing zoomed regions. * Cut, Copy, and Paste commands. PARTS * New voltage regulator template. * Improved MOSFET templates. * Ability to copy an existing part and use it as a base for a new part with similar parameter values. * New extraction algorithm. * Limitations expansion, for example, Parts accepts depletion mode JFET characteristics, etc. POLARIS * New Signal Integrity analysis tool. ****************************************************************** Part 2. Evaluation Versions ****************************************************************** The EVALUATION VERSION of the Design Center (release 5.4) has been enhanced to offer increased capacity for DIGITAL designs, so that you can experiment with a greater variety of circuits. Also new for 5.4, is the ability to model Coupled Transmission Lines. Hopefully, these will give you a good feel for the capabilities of the Design Center. The EVALUATION VERSION is a full-feature, limited-capacity version of MicroSim's Design Center product, and is available on the PC under DOS or Windows, and on the Macintosh. In general, the maximum device limits are as follows: - 10 Transistors (any combination of B, M, Q, or J devices) - 64 Analog Nodes - 2 Ideal Transmission Lines (Coupled or Uncoupled) - 2 Lossy Transmission Lines (Coupled or Uncoupled) (TOTAL of 4 T-Lines maximum, with a maximum of 2 Coupled lines) - 65 Digital Primitives, excluding STIMulus and PINDLY devices - Logic output transitions limited to 10000 - "Logic Expression" Primitives limited to 36 I/O Pins Schematics-related limitations are as follows: - Maximum of 25 parts on a page - 1 page only - A-size page only - No limit on the number of levels of hierarchy - 20 new user-defined symbols may be created and used - No printing from within the Symbol Editor - Symbols cannot be exported or imported - The number of symbol library files which can be loaded is limited to the number of files shipped, plus one Netlister limitations: - A maximum of 70 real devices (.net entries) is allowed for PSpice netlists - A maximum of 50 symbols, before packaging, may be included in the parts list for PCB layout netlists Note, however, that these limitations are maximums for a single class of devices. If, for example, you use a combination of transistors and digital primitives, the allowable number of each will be lower. ****************************************************************** Part 3. General ****************************************************************** 3.1. Version Interchangeability-Stand Alone Schematics Warning: Schematic and/or Symbol Library files which are created and/or modified using the Stand Alone version of Schematics may not be backward compatible with previous versions of Schematics. That is, if you have a 5.3 schematic that you modify using 5.4 Schematics, you may not be able to read that schematic back into 5.3 Schematics. Similarly, if you create symbols using the 5.4 Symbol Editor, these symbols may not be compatible with previous versions of Schematics (i.e., version 5.3 and before). 3.2. New Command Line Option: -i PSpice, Probe, and Schematics now support a -i command line option which allows you to specify a configuration file other than "msim.ini." To use this option, you can change the command line in the program's icon to be: <program name> -i msim54.ini If no path is specified for the ".ini" file, it is assumed to be in your Windows directory. You will need to change the PSPICECMD and PROBECMD lines in the [MICROSIM] section of "msim54.ini" to also use -i msim54.ini. ****************************************************************** Part 4. PSpice ****************************************************************** 4.1. PSpice Command Line Options The PSpice command line can contain one or more of the following command line options: -bf<flush interval> determines how often (in minutes) PSpice will flush the Probe data file to disk. This is useful when a long simulation is left running and the machine crashes or is rebooted. In this case, the data file will be readable up to the last flush. The default is to flush every 10 minutes. The <flush interval> can be set to a number of minutes between 0 and 1440. A value of zero means to never flush. -bn determines the number of buffers to potentially allocate for the Probe data file. Zero buffers means to do all writing directly to disk. Allocating a large number of buffers can speed up a large simulation, but will increase memory requirements. Exceeding physical memory will either slow down the simulation, or will make it fail. -bs determines the size of the individual buffers for writing the Probe data file. Using a larger buffer size can reduce execution time, but at the expense of increasing the memory requirements. The values for the buffer files work as follows: option -bs0 -bs1 -bs2 -bs3 -bs4 -bs5 -bs6 value 256 512 1024 2048 4096 8192 16384 4.2. PWL Form for I and V Devices The general form for "I" and "V" devices is written incorrectly in the Circuit Analysis Reference Manual. The correct form is: For Current ("I" devices): PWL [TIME_SCALE_FACTOR=<time scale factor>] + [VALUE_SCALE_FACTOR=<value scale factor>] (<tn> <in>)* + [[REPEAT FOR <n>] (<tn> <in>)* [ENDREPEAT]]* + [[REPEAT FOREVER] (<tn> <in>)* [ENDREPEAT]]* For Voltage ("V" devices): PWL [TIME_SCALE_FACTOR=<time scale factor>] + [VALUE_SCALE_FACTOR=<value scale factor>] (<tn> <vn>)* + [[REPEAT FOR <n>] (<tn> <vn>)* [ENDREPEAT]]* + [[REPEAT FOREVER] (<tn> <vn>)* [ENDREPEAT]]* The keywords TIME_SCALE_FACTOR= and/or VALUE_SCALE_FACTOR= must precede the value of the time scale factor and/or value scale factor. 4.3. PWL Syntax Note that parentheses are not required for the time/value data pairs. Parentheses have been used in the documentation examples for readability, only. The example of the PWL data file "triangle.in" included in the Circuit Analysis Reference Manual discussion inadvertently includes leading "+" signs. These should be omitted. 4.4. PWL Usage Limitations The Circuit Analysis Reference Manual (Chapter 4, "Analog Devices and Libraries") states that the PWL form may be described by up to 3995 pairs of data points. The limitation is now approximately 1000 data pairs for PC and Macintosh systems, while the number of data points for the Sun is still virtually unlimited. (Refer to the discussion of the PWL form under "V Devices" and "I Devices.") If you need to use more than 1000 data points, you may still use the FILE parameter to specify the name of a file which contains the data points. Note, however, that the file form does not support repeating loops. 4.5. New Digital Simulator Operation PSpice no longer terminates the simulation when a voltage is out of range on a digital input pin. Instead, it now produces a simulation warning message and uses the state whose voltage range is closest to the input voltage. The message will appear in the output file and can be displayed graphically with the Windows version of Probe. 4.6. New "O" Device Parameter and Operation Refer to the discussion of the digital "O" device in Chapter 5, section 5.1.4.2, of the Circuit Analysis Reference Manual. The following should be added to Table 70, Digital Output Model Parameters: Parameter Description Default --------- ------------------------------------- ------- SXNAME State applied when the interface node "?" voltage falls outside all ranges. In the same section, replace the paragraph beginning "The state of the node is determined..." with: The process of converting the input node voltage to a logic state begins by first obtaining the difference in voltage between the <interface node> and the <reference node>. As you can see, the DOUTPUT model defines a voltage range, from SxVLO to SxVHI, for each state. If the input voltage is within the range defined for the current state, no state change occurs. Otherwise, PSpice searches forward through the model, starting with the current state, to find the next state whose voltage range contains the input voltage. This state then becomes the new state. When the end of the list (S19) is reached, PSpice wraps around to S0 and continues. If the entire model has been searched and no valid voltage range has been found, PSpice will generate a simulation warning message. Further, if the O device is interfacing with the Digital Simulator, and the SXNAME parameter has not been specified in the model, PSpice will use the state whose voltage range is closest to the input voltage. Otherwise PSpice uses SXNAME as the new state. This "circular" state searching mechanism allows hysteresis to be modeled directly. The following model statement models the input thresholds of a 7400 series TTL Schmitt-trigger input. Notice the 0.8 volt overlap between the "0" state voltage range and the "1" state voltage range. .model DO74_ST doutput ( + s0name="0" s0vlo=-1.5 s0vhi=1.7 + s1name="1" s1vlo=0.9 s1vhi=7.0 + ) Starting from the "0" state, a positive-going voltage must cross 1.7 volts to get out of the "0" state's voltage range. The next state which contains that voltage is "1". Once there, a negative-going voltage must go below 0.9 volts to leave the "1" state's range. Since no further states are defined, PSpice wraps around back to state "0", which contains the new voltage. 4.7. Digital Worst-Case Timing Analysis Enhancement A change was made to PSpice to improve accuracy during Digital Worst- Case Timing analyses of certain circuits. The change affects the results of gate primitives, LOGICEXP primitives, and PLD primitives which have ambiguous rising (R) and falling (F) levels on their inputs. Gates which are presented with simultaneous opposing R and F levels may now produce a pulse of the form 0->R->0, or 1->F->1. For example, a two-input AND gate with the signals _____ A _____///// _____ B \\\\\_____ on its inputs may produce Y _____/////_____ on its outputs. This should be interpreted as "a possible single pulse, no longer than the duration of the R level". The actual device's output may or may not change, depending on the transition times of the inputs. In previous versions of PSpice, gates which were presented with such inputs would simply produce an unknown (X) pulse on their outputs. This change corrects a problem in Digital Worst-Case Timing simulations in certain ambiguity convergence situations. For example, an ambiguous clock drives three flip-flops, two of whose outputs drive a gate, which drives the data input for the third. ____ 1--| | CLK -----+-----|> |----+ | |____| | ___ | ____ +--| \ ____ | 0--| | | |------| | +-----|> |-------|___/ +--|> |--- | |____| | |____| | | +---------------------------+ In situations where the inputs to the gate are in opposition, PSpice now correctly realizes that the clock will always precede the arrival of the data input on the third flip-flop, even though the clock and data have overlapping ambiguities. 4.8. New Example Circuit A new example circuit is now included with PSpice. It is a digital frequency comparator, designed using the standard parts contained in the "7400.lib" library (also new for 5.4). Supporting components are included in "frqchkx.lib" and "frqchkx.slb" which are invoked through an INCLUDE within the schematic. Stimulus for this example, as well as a basic description of operating requirements, is contained in "frqchk.stm." The schematic diagram for the frequency comparator circuit is named "frqchkx.sch." There are also several supporting schematic files included. The text of the April 1993 MicroSim Newsletter article describing the operation of the circuit is included in the file "frqchk.doc" for your convenience. One change that has been included in this version of the example is that the default view of the SDL block now references the "SDLXLE" schematic, which is a LOGICEXPR-style model used to represent the random gate logic of the "State Decode Logic" (SDL) block. It utilizes the "DECODER" subcircuit (from "frqchkx.lib"). Two other views of SDL exist: the "gate level" (SDLX) and a PAL implementation (SDLPX). Use the Navigate/Push Select Block dialog to choose one of these alternative views, re-netlist the design, then re-simulate to explore these representations. ****************************************************************** Part 5. Probe ****************************************************************** 5.1. Probe Command Line Options The PSpice command line can contain one or more of the following command line options: -bn determines the number of buffers to potentially allocate for the Probe data file. Zero buffers means to do all reading directly from disk. Allocating a large number of buffers can speed up the reading of a large Probe data file, but will increase memory requirements. Exceeding physical memory will either slow down Probe, or will make it fail. -bs determines the size of the individual buffers for reading the Probe data file. Using a larger buffer size can reduce execution time, but at the expense of increasing the memory requirements. The values for the buffer files work as follows: option -bs0 -bs1 -bs2 -bs3 -bs4 -bs5 -bs6 value 256 512 1024 2048 4096 8192 16384 5.2. Marching Waveforms 5.2.1. Marching Waveforms During Multiple-Run Analyses If Marching Waveforms (Analysis/Probe Setup/Run Probe During Simulation) is enabled during a multiple run simulation (i.e., AC sweep, DC sweep, .STEP, .TEMP, etc.), only the data for the first run will be displayed in Probe. To view the family of curves for all runs, close the data file using File/Close, then reload it using File/Open. Probe will then prompt for the sections to be loaded, and the requested traces will be displayed. 5.2.2. Known Problems 1. Digital waveforms may march too slowly to be useful. 2. Disable the DOS "share" command when using the marching waveforms feature. 5.3. Cut, Copy, and Paste Commands 5.3.1. Using the Clipboard Data The Edit/Cut and Edit/Copy commands are used to place Probe data in the clipboard. The following Clipboard Display options are then available for viewing of the data: Display/Display Text: Displays only the Probe trace name Display/Text: Displays the data pairs in a proportional font Display/OEM Text: Displays the data pairs in a monospaced font If you want to store the Probe data points as an ASCII file, you should paste the data from the Clipboard into a text editor of your choice. (Note that if you try to save the data directly from within the Clipboard Viewer program some spurious clipboard file data may be included at the beginning of the file.) 5.3.2. Pasting Objects from the Tools/Label Menu The description of this function in the Circuit Analysis Reference Manual is inaccurate. The last paragraph on page 288 (section 7.4.1.2) should read as follows: "Pasted objects from the Tools/Label Menu (see page 307) will be placed at the same x and y coordinates that they were at when they were Cut or Copied. Once an item from the Label Menu is pasted, it can then be selected and moved around the plot window." 5.4. Goal Function File Included with this release is a file, "msim.gf," which provides various examples of goal functions for use with Probe. The file is in ASCII format and may be viewed with a text editor. If you already have a goal function file you may wish to append parts of "msim.gf" to your existing "probe.gf" file. If you do not have a goal function file, you can rename the file to "probe.gf" for use with Probe. ****************************************************************** Part 6. Schematics ****************************************************************** 6.1. Using Schematics Created with Version 5.3 and Earlier Version 5.4 fixes a problem with moving attributes on flipped and/or rotated parts. The attributes would sometimes "bounce" to a position other than where the mouse was clicked. However, it does require that schematics created with version 5.3 (or earlier) of Schematics be run through a conversion process. This conversion process will correct the locations of attributes on flipped/rotated parts so that they display at the same locations relative to the parts as they did in the version with which they were created. If the conversion is not done, some attributes in your schematic may display/print at different locations than when it was created. You will then need to move the attributes manually. Conversion will be done whenever a schematic written with version 5.3 or earlier of Schematics is loaded (using File/Open) or pushed into (using Navigate/Push or double-clicking on the hierarchical part). You will be prompted first as to whether or not you wish to do the conversion. After the conversion is complete, you MUST save the schematic for the conversion to be permanent. If you do not wish to convert your schematics (and don't want to be bothered by the prompt), add CONVERSION=OFF to the [SCHEMATICS] section of your "msim.ini" file. 6.2. Schematics Netlister The Schematics netlister no longer puts full path names in the .include statements for the ".als" and ".net" files. This should make it easier to copy designs to another directory and resimulate. 6.3. New Symbols 6.3.1. STIM Symbols - "source.slb" Four STIM symbols have been added to the "source.slb" library file: STIM1, STIM4, STIM8, and STIM16. STIM1 is for use where only a single node is being driven. The other three symbols are used to provide stimuli to buses that are 4, 8, and 16 bits wide. Use the DRAW/GET NEW PART menu command, then connect the STIM symbol to the wire (for STIM1) or the bus (for STIM4, STIM8, and STIM16) to which the stimulus is to be applied. Double click on the symbol to edit the attributes. Generally, only the FORMAT, TIMESTEP, and COMMAND attributes need to be modified. Sixteen COMMAND variables are available, Normally each command attribute will contain only one command lime. It is possible to enter more than one command line per COMMAND attribute by placing \n+ between the command lines. The "n" must be lower case and there are no spaces between the characters. (A space may precede or follow the group.) For more information on the STIM device, refer to the Stimulus Devices discussion in the "Digital Devices and Libraries" chapter of the Circuit Analysis Reference Manual. 6.3.2. PRINT AND PLOT Symbols - "special.slb" Six new symbols have been added to "special.slb" in order to expand the .PRINT and .PLOT options available from Schematics. VPRINT1 -- generates a print table for the voltage at a single node of interest. VPRINT2 -- generates a print table for the voltage differential between two nodes. VPLOT1 -- generates a "line printer" plot for the voltage at a single node of interest. VPLOT2 -- generates a "line printer" plot for the voltage differential between two nodes. IPRINT -- generates a print table for the current through a cut in the net. IPLOT -- generates a "line printer" plot for the current through a cut in the net. Single terminal devices can be connected directly to the node of interest. Voltage differential .PRINT and .PLOT devices should be connected across the two nodes of interest. IPRINT and IPLOT symbols should be inserted into the circuit in series (i.e. break the circuit to insert the IPRINT or IPLOT), because they are current meters. Double-click on the symbol. Select at least one analysis type (TRAN, AC, or DC depending on the type(s) of analysis being performed). If AC is selected, then one or more output formats may be selected (MAGnitude, PHASE, REAL, IMAGinary, or DB). To select an analysis type and/or output format, double-click on the attribute and give it any value. 'Y' for 'Yes' or the numeral 1 are common values, but anything will work. Multiple analysis types may be selected provided that those analysis types are being performed. If AC is selected, then multiple formats may be selected. If no analysis types are selected, the default is transient. If AC is selected, but no output formats are selected, then the default is the magnitude of the voltage at the connected node. To generate a print table of the magnitude and phase of the voltage at the connected node resulting from the AC analysis you might use the VPRINT1 symbol with the AC, MAG, and PHASE attributes enabled. For more information on generating print tables and/or "line printer" plots, see the discussion of .PRINT and .PLOT in the COMMANDS chapter of the Circuit Analysis Reference Manual. 6.3.3. Analog Devices with Visible Pin Numbers - "analog_p.slb" A new symbol library file, "analog_p.slb," has been added for those who wish to have visible pin numbers on the analog devices R, L, C, R_VAR, and C_VAR. Analog_p.slb must be configured by adding it to the list of configured symbol library files before or in place of the file "analog.slb." From within the Schematic Editor, do the following: 1. Select Configuration/Editor Configuration/Library Settings. 2. Select (left click) on "analog.slb," enter "analog_p" for File Name, clear the Package check box and select the Symbol check box, click on the ADD button, and click on the OK button to approve the changes. 3. Optionally remove the reference to "analog.slb" by selecting it and then clicking on the Delete button. The symbols in "analog_p.slb" will now be used by the Schematic Editor instead of those in "analog.slb." 6.3.4. Time-Dependent Switches Two new symbols and associated models representing time-dependent switches have been added to "misc.slb" and "misc.lib." The switches are named Sw_tClose and Sw_tOpen, and they have the following attributes: Attribute Description Default Value --------------------------------------------------------------------- tOpen and Time (Time at which transition begins) 0 tClose Note: tOpen and tClose apply to the respective model/symbol. They have the same definition and default value. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ttran Transition time (Time required for 1 us the switch to change states) Rclosed Closed state resistance 0.01 Ohm Ropen Open state resistance 1 Mega-Ohm Note: ttran, Rclosed, and Ropen are common to both models/symbols. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 6.4. Autosave The [SCHEMATICS] section of the "msim.ini" file may contain an entry specifying the save interval for the Autosave feature. This entry has the following form: AUTOSAVE=<n> where <n> is the autosave interval in minutes. Refer to the Schematic Capture User's Guide for more information on the Autosave feature. 6.5. Marker Support Marker support of PSpice and Probe output variables has been added for AC analysis-specific elements, such as M (magnitude), DB (magnitude in decibels), P (phase), and G (group delay). 6.5.1. Implementation The Schematic Editor Markers menu provides the following new command: Mark Advanced: Mark Advanced displays a list of the available symbols in the Marker Symbol Library file "marker.slb." This allows you to place markers to view the magnitude in decibels (dB), phase, and/or group delay. The markers for dB, phase, group delay, real, and imaginary waveform characteristics can be used instead of the built-in Probe functions provided in output variable expressions 6.6. Probe Setup Options in Schematics You can now specify whether waveforms will be shown automatically when Probe is started from Schematics (either automatically after a simulation, during auto-update, or using the Analysis/Run Probe command.) The Analysis/Probe Setup command has been changed to allow you to specify one of the following: 6.6.1. Restore Last Probe Session If this option is enabled, Probe will restore the display using the display control setup from the previous Probe session. 6.6.2. Show All Markers If this option is enabled, traces will be displayed in Probe wherever markers are located in the schematic. (i.e., performs a Markers/Show All) 6.6.3. Show Selected Markers If this option is enabled, traces will be displayed in Probe wherever there any selected markers on the current page of the schematic (i.e., performs a Markers Show/Selected) 6.6.4. None If this option is enabled, no traces will be displayed automatically when Probe is started. 6.7. Changes to the "msim.ini" File The following configuration items have been moved from the [SCHEMATICS] section to the [MICROSIM] section: PROBECMD PSPICECMD WINDOWSPSPICE EDITOR "Marker.slb" should no longer be included in the list of libraries. If it is, you will get a warning when you start up Schematics: "marker libraries should not be in configured list." This is just a warning; you can continue to use Schematics. 6.8. Accelerator Key Changes The accelerators for Cut, Copy, Paste have been changed to <Ctrl X>, <Ctrl C> , <Ctrl V> to be consistent with Windows 3.1 standards. The old accelerators (<Delete>, <Ctrl Insert>, <Ctrl Shift>) are still supported. Schematic Editor: Command New Old -------- -------- ----------- <Ctrl N> Zoom/Normal Navigate/Create Page Symbol Editor: Command New Old -------- ------------ ----------- <Ctrl N> Zoom/Normal Part/New <Ctrl C> Edit/Copy Part/Copy <Ctrl E> Package/Edit <none> <Alt R> none Return to Schematic 6.9. Font-Related Issues 6.9.1. Using the RASTERFONT=ON/OFF Switch If the line RASTERFONT=ON is included in your "msim.ini" file, it causes the Helvetica font to be used instead of the modern font for display in Schematics. This will cause rotated text to appear vertically versus being rotated on its side. If your symbols and schematics use rotated text, setting this item to ON may cause problems with positioning text. For this reason, we suggest using the RASTERFONT=OFF switch setting. 6.9.2. Using Adobe Type Manager with Schematics If you have Adobe Type Manager installed and are using Schematics, you may encounter problems with how rotated text is displayed. We recommend that you check the "ATM.ini" file and comment out the line Modern=Helvetica in the [ALIASES] section. If this is not done, rotated text may be positioned differently on the display versus on hard copies. We also do not recommend using the FONTTYPE=ADOBE setting in your "msim.ini" file at this time as it has the same problem. ****************************************************************** Part 7. Device Equations Option ****************************************************************** Use of the Device Equations option is described in Appendix A of the Circuit Analysis Reference Manual. Please note the following corrections the compiler/linker requirements: The compiler/linker requirement for the Windows version has been changed from the Microsoft C compiler to the WATCOM C/386 compiler. Specifically, the information in Appendix A of the Circuit Analysis Reference Manual should read as follows: Page 375: A.1, the note should read: "...you must have the WATCOM C/386, version 9.01.e compiler (for the Windows version), or the Sun C compiler (for the Sun)." Page 379, A.3.1 should now read: "The object and source files necessary to make the Windows version of PSpice ("wpspice.exe") have been installed in the subdirectory DEVEQU. A batch file, "devequ.bat," is included to compile and link the program. "The object code has been compiled with the WATCOM C/386 compiler, version 9.01.e. This compiler comes with the necessary Windows SDK components to compile PSpice. "Once you have built WPSPICE.EXE, you should rename it to avoid confusion with the original version. Then, copy it to the same directory as the rest of the Design Center programs. You can then add it to the Design Center group in the Program Manager so that it can be invoked from an icon." ****************************************************************** Part 8. Polaris Signal Integrity ****************************************************************** Translating Alphanumeric Pin Numbers from PCAD Layout Files: You may encounter problems simulating parasitics extracted from PDIF (P- CAD) layout files. Problems with regenerating the netlist can occur if any of the P-CAD library components used in the design have alphanumeric pin numbers and the corresponding part in the Schematics Symbol Library has numeric pin numbers. You can tell if this is the case by inspecting the SPKG constructs contained in the component definitions (COMP_DEF construct) in your PDIF layout file. If you find an SPKG construct that contains an Apn construct, you must ensure that the pin names contained in the P constructs of the pin definitions for the part (PIN_DEF construct) are numeric (i.e., not alphanumeric). If the pin names contained in the P constructs are numeric, you should not have a problem. However, if the pin names in the P constructs are alphanumeric, and the Apn construct contains only numeric pin numbers, you can add the following commands to the special net file, "*.snf." .PDIF USEAPN (The .snf file was created when Schematics initialized the database translation.) This forces the translator to use the pin numbers contained in the Apn construct instead of those in the P constructs. If both the P and Apn constructs contain alphanumeric pin numbers, then you may have to edit the component definition so that the pin numbers map correctly between P-CAD and Schematics. Also, if both the P and Apn constructs contain alphanumeric pin numbers and there is an SP construct present as well in the SPKG construct, your file contains a syntax error. This means that most pin number mapping problems for PDIF files can be resolved by editing the .snf file as described above. ****************************************************************** Part 9. Intel IBIS Model Support ****************************************************************** A library of Intel's IBIS models will be available in July 1993. They are Intel's Pentium (TM) 82430 PCIset I/O buffer models. These highly accurate driver/receiver buffer models include effects such as switching times, nonlinear transfer characteristics, and package parasitics. They allow designers to perform signal-integrity simulation of I/O interconnects. An example of an IBIS model follows. Note that the parameters used in this subcircuit are from IBIS data published by Intel. IBIS ESC2 Buffer Model - Worst-Case * *** Worst-case: max ramp time, max package parasitics, * max die Cout, min output currents * * The Enable is active high * * * * Input Output VCC GND Enable .subckt ESC2_W 100 200 300 400 500 + PARAMS: + Cout = 7.2pf ; die capacitance at output + Co_pkg = 2.8pf ; package bond wire and lead ; capacitance at output + Lo_pkg = 15.1nH ; package bond wire and lead ; inductance at output + Ro_pkg = 0.405 ; package bond wire and lead ; resistance at output + dVdt_r = {4.75/1.45} ; output rise time + dVdt_f = {4.75/1.61} ; output fall time * * ******* Parameters ******* .PARAM Rtr = { (1/dVdt_r) * 1e5} .PARAM Rtf = { (1/dVdt_f) * 1e5 } .PARAM Vinh = 1.56v ; Input high threshold voltage .PARAM Vinl = 1.47v ; Input low threshold voltage * * ******* Input and Enable Threshld ********************** Ein_thr_dn 800 0 VALUE = {TABLE(V(100,400), + Vinl, 0, + Vinl+1e-6, 1)} * Ein_thr_up 810 0 VALUE = {TABLE (V(100,400), + Vinh-1e-6, 1, + Vinh, 0)} * Ein_thr 530 0 VALUE = {TABLE (V(500,0), + Vinl, 0, + Vinh, 1)} * Edn 820 0 VALUE = {LIMIT(V(800), 0, V(530))} * Eup 830 0 VALUE = {LIMIT(V(810), 0, v(530))} * Rdum1 530 0 1G Rdum2 800 0 1G Rdum3 810 0 1G Rdum4 820 0 1G Rdum5 830 0 1G * * ******** Rise & Fall Time ******* * Gramp_dn 840 400 VALUE={v(840,400) / (abs(v(840,400) * Rtf + + V(820,400) * 1e7) + 1e-4) } Cramp_dn 840 400 0.01pf * ERchrg_dn 840 220a VALUE={I(Vchrg_dn) * (abs(v(830) * + 1e+9)+1e-4)} Vchrg_dn 220a 220 cchrg_dn 840 220 1f * Gramp_up 300 850 VALUE = {v(300,850) / (abs(v(300,850) * Rtr + + V(830,400) * 1e7) + 1e-4)} Cramp_up 850 300 0.01pf * ERchrg_up 850 220b VALUE = {I(Vchrg_up) * (abs(V(820) * 1e9) + + 1e-4)} Vchrg_up 220b 220 cchrg_up 850 220 5f * * ******* Output Pulldown ******* Esw_dn 240 0 VALUE = { TABLE(v(840), + 4.5-1e-5, 1, + 4.5v, 0) } * Rout_dn 220 400 1 Gadj_dn 220 400 VALUE = {V(280,220)} Elim_dn 280 400 VALUE = {LIMIT(v(260), -v(240)*1e3, + v(240)*1e3)} * * The following defines the I/V curve of the pulldown * structure: Epwl_dn 260 0 TABLE {V(220,840)} + -5.0v, -110m + -4.0v, -107m + -3.0v, -103m + -2.0v, -91m + -1.0v, -57m + 0.0v, 0m + 0.5v, 31m + 1.0v, 57m + 1.5v, 76m + 2.0v, 91m + 2.5v, 100m + 3.0v, 103m + 3.5v, 105m + 4.0v, 107m + 4.5v, 109m + 5.0v, 111m + 10.0v, 120m Rdum6 240 0 1G Rdum7 260 0 1G Rdum8 280 400 1G * ******* Output clamp to GND ******* ** The following defines the I/V curve of the clamping ** diode connected to GND: Ggnd_out 220 400 TABLE {V(220,400)} + -5.0v, -1725m + -1.0v, -110m + -0.9v, -70m + -0.8v, -35m + -0.7v, -5m + -0.6v, 0u + -0.5v, 0u + 0.0v, 0u + 10.0v, 0u * ******* Output pullup ******* ***** Esw_up 230 0 VALUE = {TABLE(V(850), + 0.5v, 0, + 0.5+1e-5, 1 )} Rout_up 300 220 1 Gadj_up 300 220 VALUE={V(220,270)} Elim_up 300 270 VALUE={LIMIT(V(0,250), -V(230)*1e3, + V(230)*1e3)} * * The following defines the I/V curve of the pullup * structure: Epwl_up 250 0 TABLE={V(850,220)} + -5.0v, 57m + -4.0v, 54m + -3.0v, 50m + -2.0v, 40m + -1.0v, 23m + 0.0v, 0m + 0.5v, -13m + 1.0v, -23m + 1.5v, -33m + 2.5v, -46m + 3.0v, -50m + 3.5v, -52m + 4.5v, -55m + 5.0v, -57m + 10.0v, -66m Rdum9 230 0 1G Rdum10 250 0 1G Rdum11 270 300 1G * ******* Output clamp to VCC * The following defines the I/V curve of the clamping diode * connected to VCC: GVcc_out 220 300 TABLE {V(300,220)} + -5.0v, 970m + -1.0v, 74m + -0.9v, 52m + -0.8v, 30m + -0.7v, 4m + -0.6v, 0m + -0.5v, 0m + -0.4v, 0m + 0v, 0m * ******* Output Package ******* ** Cout_pkg 200 400 {Co_pkg} Rout_pkg 200 210 {Ro_pkg} Lout_pkg 210 220 {Lo_pkg} Rout_snb 210 220 100 Cout_die 220 400 {Cout} ******* End of Subcircuit ******* **** .ENDS ESC2_W These models are not part of the libraries shipped with the 5.4 release. If you currently have version 5.4 of the Design Center and would like to receive these models, please send your business card, with your program ID number written on the back, to: MicroSim Corporation Pre-release IBIS Models 20 Fairbanks Irvine, CA 92718 or call 1-800-245-3022 with that information. The above example model is also available on MicroSim's BBS. ****************************************************************** Part 10. New Libraries and Devices ****************************************************************** This section lists the new libraries and devices added to the 5.4 release which are not documented in the documentation set. 10.1. New Library - "AMP.LIB" This library provides the following connector models: - C - CHHDSM/AMP CHHDSAL/AMP CHS1B/AMP CHS1SB/AMP CHHDSA/AMP CHHDSBL/AMP CHS1C/AMP CHS1SC/AMP CHHDSB/AMP CHHDSCL/AMP CHS1D/AMP CHS1SD/AMP CHHDSC/AMP CHHDSDL/AMP CHS1ML/AMP CHS1SML/AMP CHHDSD/AMP CHHDSEL/AMP CHS1AL/AMP CHS1SAL/AMP CHHDSE/AMP CHHDSFL/AMP CHS1BL/AMP CHS1SBL/AMP CHHDSF/AMP CHHDSGL/AMP CHS1CL/AMP CHS1SCL/AMP CHHDSG/AMP CHHDSHL/AMP CHS1DL/AMP CHS1SDL/AMP CHHDSH/AMP CHS1M/AMP CHS1SM/AMP CHHDSML/AMP CHS1A/AMP CHS1SA/AMP - E - EEC4M/AMP EEC5B/AMP EISAAL/AMP ETCBL/AMP EEC4A/AMP EEC5C/AMP EISAEL/AMP ETCCL/AMP EEC4B/AMP EEC5ML/AMP EISABL/AMP EEC4C/AMP EEC5AL/AMP EISAFL/AMP EEC4ML/AMP EEC5BL/AMP ETCM/AMP EEC4AL/AMP EEC5CL/AMP ETCA/AMP EEC4BL/AMP EISAA/AMP ETCB/AMP EEC4CL/AMP EISAE/AMP ETCC/AMP EEC5M/AMP EISAB/AMP ETCML/AMP EEC5A/AMP EISAF/AMP ETCAL/AMP - F - FB2MM/AMP FB2MC/AMP FB2MAL/AMP FB2MDL/AMP FB2MA/AMP FB2MD/AMP FB2MBL/AMP FB2MB/AMP FB2MML/AMP FB2MCL/AMP - H - HDI3M/AMP HDI4M/AMP HDI4SAL/AMP HM7M/AMP HDI3A/AMP HDI4A/AMP HDI4SBL/AMP HM7A/AMP HDI3B/AMP HDI4B/AMP HDI4SCL/AMP HM7B/AMP HDI3C/AMP HDI4C/AMP HDI4SDL/AMP HM7C/AMP HDI3ML/AMP HDI4D/AMP HM5M/AMP HM7D/AMP HDI3AL/AMP HDI4ML/AMP HM5A/AMP HM7E/AMP HDI3BL/AMP HDI4AL/AMP HM5B/AMP HM7ML/AMP HDI3CL/AMP HDI4BL/AMP HM5C/AMP HM7AL/AMP HDI3SM/AMP HDI4CL/AMP HM5D/AMP HM7BL/AMP HDI3SA/AMP HDI4DL/AMP HM5E/AMP HM7CL/AMP HDI3SB/AMP HDI4SM/AMP HM5ML/AMP HM7DL/AMP HDI3SC/AMP HDI4SA/AMP HM5AL/AMP HM7EL/AMP HDI3SML/AMP HDI4SB/AMP HM5BL/AMP HSCEM/AMP HDI3SAL/AMP HDI4SC/AMP HM5CL/AMP HSCEML/AMP HDI3SBL/AMP HDI4SD/AMP HM5DL/AMP HDI3SCL/AMP HDI4SML/AMP HM5EL/AMP - I - ISAM/AMP ISAML/AMP - L- LPG27A/AMP LPG27AL/AMP LPG27B/AMP LPG27BL/AMP LPG27C/AMP LPG27CL/AMP - M - MD5S25M/AMP MI25SML/AMP MSRAAL/AMP MS73M/AMP MD5S25ML/AMP MI50M/AMP MSRABL/AMP MS73A/AMP MD5S32M/AMP MI50ML/AMP MSRACL/AMP MS73B/AMP MD5S32ML/AMP MI50SM/AMP MSRADL/AMP MS73C/AMP MEPGA/AMP MI50SML/AMP MS43A/AMP MS73D/AMP MEPGB/AMP MODU39M/AMP MS43B/AMP MS73ML/AMP MEPGC/AMP MODU39ML/AMP MS43C/AMP MS73AL/AMP MEPGAL/AMP MSRAM/AMP MS43D/AMP MS73BL/AMP MEPGBL/AMP MSRAA/AMP MS43ML/AMP MS73CL/AMP MEPGCL/AMP MSRAB/AMP MS43AL/AMP MS73DL/AMP MI25M/AMP MSRAC/AMP MS43BL/AMP MI25ML/AMP MSRAD/AMP MS43CL/AMP MI25SM/AMP MSRAML/AMP MS43DL/AMP - S - SES5M/AMP SES5ML/AMP - T - TBC4M/AMP TBC5B/AMP TBC6B/AMP TPG35A/AMP TBC4A/AMP TBC5C/AMP TBC6C/AMP TPG35B/AMP TBC4B/AMP TBC5D/AMP TBC6D/AMP TPG35C/AMP TBC4C/AMP TBC5E/AMP TBC6E/AMP TPG35AL/AMP TBC4D/AMP TBC5ML/AMP TBC6F/AMP TPG35BL/AMP TBC4ML/AMP TBC5AL/AMP TBC6ML/AMP TPG35CL/AMP TBC4AL/AMP TBC5BL/AMP TBC6AL/AMP TPI35A/AMP TBC4BL/AMP TBC5CL/AMP TBC6BL/AMP TPI35B/AMP TBC4CL/AMP TBC5DL/AMP TBC6CL/AMP TPI35C/AMP TBC4DL/AMP TBC5EL/AMP TBC6DL/AMP TPI35AL/AMP TBC5M/AMP TBC6M/AMP TBC6EL/AMP TPI35BL/AMP TBC5A/AMP TBC6A/AMP TBC6FL/AMP TPI35CL/AMP - Z - ZPSLM/AMP ZPSLML/AMP ZPSLA/AMP ZPSLAL/AMP ZPSLB/AMP ZPSLBL/AMP ZPSLC/AMP ZPSLCL/AMP ZPSLD/AMP ZPSLDL/AMP 10.2. New Devices - "LIN_TECH.LIB" Library This library provides the following opamp models: LM10C/LT LT1200/LT LT1222/LT LT1001S8/LT LT1201/LT LT1223/LT LT1007CS/LT LT1202/LT LT1224/LT LT1028CS/LT LT1208/LT LT1225/LT LT1037CS/LT LT1209/LT LT1226/LT LT1187/LT LT1211/LT LT1227/LT LT1189/LT LT1212/LT LT1228/LT LT1190/LT LT1213/LT LT1229/LT LT1191/LT LT1214/LT LT1230/LT LT1192/LT LT1215/LT LT1252/LT LT1193/LT LT1216/LT LT1253/LT LT1194/LT LT1217/LT LT1254/LT LT1195/LT LT1221/LT LT318A/LT 10.3. New Devices in Other Libraries The following libraries also contain new devices. Refer to the appendix in the Circuit Analysis Reference Manual for specific device names. AMP.LIB * HARRIS.LIB ANLG_DEV.LIB LINEAR.LIB APEX.LIB LIN_TECH.LIB * BURR_BRN.LIB NAT_SEMI.LIB COMLINR.LIB POLYFET.LIB ELANTEC.LIB (*)Additional parts not listed in the Circuit Analysis Reference Manual are listed in previous sections of this file. ****************************************************************** Part 11. MODTOMDT Utility ****************************************************************** MODTOMDT is a utility program to convert PSpice model files or library files containing PSpice models to MDT files in Parts format. The MDT files generated will be compatible with other MDT files generated by Parts. Currently, the following device types are supported: DIODE JFET BJT MOSFET (LEVEL 3) The following lists features and usage of this utility: 1. Allow users to load a model file into Parts and see the performance curves of the model. 2. Allow users to perform a "what-if" analysis when they change the model parameters in Parts. 3. Allow our users to modify/update the model by entering screen data into the Parts program and re-fit some model parameters Usage: modtomdt [options] <infile> An input file must be provided. This could be a single model file, or it could be a .LIB file that contains many .MODEL statements. Command line options: -h provide a summary of usage -n force all answers to program queries to 'No' -y force all answers to program queries to 'Yes' Each .MODEL statement in a file will result in an individual MDT file. If the output MDT file already exists, the user is prompted to confirm overwriting the existing file. An example: A user wants to use a device, "A," for PSpice simulation, but cannot find the model in the library. However, a similar device, "B," is in the library. Here is the procedure for creating the A.MDT file using Parts and the B device: 1. Copy the model for device B from the appropriate library file to a file <infile>. (The model begins with a .MODEL statement.) 2. Run MODTOMDT <infile> to create B.MDT. 3. Rename B.MDT to A.MDT. 4. Run Parts, and load A.MDT. 5. Modify/Add data using the Parts program, then generate the file A.MOD.